FifthGen™ Hybrid Computing Platform

The FifthGen Parallel Processor is a tree-structured network of processors designed to provide significant performance improvement in the execution of very large time-consuming problems, such as speech recognition and pattern recognition. Earlier versions of tree-structured machines were first designed at Columbia University under DARPA contracts.

FGC’s patented technology includes a novel method and system for interconnecting large numbers of microprocessors in an array formed as a binary tree or similar topology by utilizing an FPGA-based bus controller at each processor node. We believe this method is included in a wide number of computer systems now deployed throughout the world.

Binary Tree Architecture

In the binary tree architecture, each Blade Processor Element (BPE) represents a node that branches to two connected nodes, sometimes referred to as the left child and the right child, each of which continues on to the next level. This architecture is especially suited to perform compute–intensive “approximate-match-search” functions that must compare/compute an ‘unknown input’ to a large set of known possibilities, allowing for various forms of distortion and/or incompleteness in the unknown.

FifthGen Parallel Systems Software

The goal of using parallel processing is to solve a given problem in less time than it takes to solve the same problem on a single processor. Ideally, two processors should take half the time that two processors take. And so on, as you add more processors, you should be able to reduce processing time accordingly. For many applications, the binary tree architecture is the most efficient parallel processing method.

The higher level system software is based on a simple paradigm. Each processor will run the same program. However, each processor will be given a different data set to solve the problem. As each processor reaches a resolution, it transmits its result back through the tree to the main host processor. These four steps are described as (1) Broadcasting of instructions and data, (2) Parallel execution, (3) Resolution, and (4) Reporting.

Here is a real example. A known set of patterns are distributed among the processors (BPEs). The broadcast function is used to simultaneously send the ‘unknown input pattern’ from the Host computer to all of the BPEs where the search function is to be performed. The resolve function causes the best match to be filtered back through the tree from the farthermost BPEs to successive levels of BPEs until the best match reaches the Host computer.  BPEs at each level, except for those at the farthermost positions, choose the best match from those received to be sent toward the Host computer.

The architecture is scalable.  Scalability of a multiprocessor computer system is achieved if the number of BPEs can be easily changed without having to make changes to application software or the system software in each Blade Processing Element.  The binary-tree configuration simply grows true to its binary form as the system is expanded.  The effect of scaling is transparent to the application software except that there is an increase in computer power and memory capacity.  The transfer path adds only one tree level for each doubling of the number of BPEs.

Binary Tree Advantages

The efficiency of a parallel processor can be evaluated by measuring the percent utilization of each processor for the problem being solved.  But as processors and memory become less expensive, the cost of communications channels and the cost of programming time become increasingly critical considerations.

The FifthGen binary tree approach excels in:

  1. Simplicity of programming, since the FifthGen System does not require a  non-standard “parallel” programming language in order to set up the parallel processing version of the user’s program.
  2. Scalability, since the FifthGen System is scalable in increments with a four-processor module, in the field, without requiring changes in the application or system software.
  3. Modularity, which allows the FifthGen System to interconnect to networks using standard network protocols.
  4. Fault tolerance, since multiple FifthGen System modules can be configured to provide increased reliability.

Parallel Processing Patents

Fifth Generation Computer Corporation (FGC) is the owner of three parallel processing patents, all related to multiprocessing on arrays of processors. Two of FGC's patents were first assigned to Columbia University under the terms of Defense Department regulations since the original research was funded by the US Navy. In 1996, the patents were assigned to FGC as recorded in the US Patent Office. The third patent for a parallel processor was issued in December, 1999 to James Maddox, FGC Director of Engineering, and assigned to the Company.


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